The E Hardware Verification Language

I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verification language within the context of coverage driven verification methodology. I hope it will help the reader und- stand the many important and interesting topics surrounding hardware verification. Yoav Hollander Founder and CTO, Verisity Inc. Preface This book provides a detailed coverage of the e hardware verification language (HVL), state of the art verification methodologies, and the use of e HVL as a facilitating verification tool in implementing a state of the art verification environment. It includes comprehensive descriptions of the new concepts introduced by the e language, e language syntax, and its as- ciated semantics. This book also describes the architectural views and requirements of verifi- tion environments (randomly generated environments, coverage driven verification environments, etc. ), verification blocks in the architectural views (i. e. generators, initiators, c- lectors, checkers, monitors, coverage definitions, etc. ) and their implementations using the e HVL. Moreover, the e Reuse Methodology (eRM), the motivation for defining such a gui- line, and step-by-step instructions for building an eRM compliant e Verification Component (eVC) are also discussed.

Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplishment, have you ever had someone ask you, "Are you good or are you just lucky?"? Many design projects depend on blind luck in hopes that the chip will work. Other's, just adamantly rely on their own abilities to bring the chip to success. ill either case, how can we tell the difference between being good or lucky? There must be a better way not to fail. Failure. No one likes to fail. ill his book, "The Logic of Failure", Dietrich Domer argues that failure does not just happen. A series of wayward steps leads to disaster. Often these wayward steps are not really logical, decisive steps, but more like default omissions. Anti-planning if you will, an ad-hoc approach to doing something. To not plan then, is to fail.

Verification is increasingly complex, and SystemVerilog is one of the languages that the verification community is turning to. However, no language by itself can guarantee success without proper techniques. Object-oriented programming (OOP), with its focus on managing complexity, is ideally suited to this task. With this handbook—the first to focus on applying OOP to SystemVerilog—we’ll show how to manage complexity by using layers of abstraction and base classes. By adapting these techniques, you will write more "reasonable" code, and build efficient and reusable verification components. Both a learning tool and a reference, this handbook contains hundreds of real-world code snippets and three professional verification-system examples. You can copy and paste from these examples, which are all based on an open-source, vendor-neutral framework (with code freely available at www.trusster.com). Learn about OOP techniques such as these: Creating classes—code interfaces, factory functions, reuse Connecting classes—pointers, inheritance, channels Using "correct by construction"—strong typing, base classes Packaging it up—singletons, static methods, packages

As part of the Modern Semiconductor Design series, this book details a broad range of e-based topics including modelling, constraint-driven test generation, functional coverage and assertion checking.

Describes a small verification library with a concentration on user adaptability such as re-useable components, portable Intellectual Property, and co-verification. Takes a realistic view of reusability and distills lessons learned down to a tool box of techniques and guidelines.

What’s this AOP thing anyway, really—when you get right down to it—and can someone please explain what an aspect actually is? Aspect-Oriented Programming with the e Verification Language takes a pragmatic, example based, and fun approach to unraveling the mysteries of AOP. In this book, you’ll learn how to: • Use AOP to organize your code in a way that makes it easy to deal with the things you really care about in your verification environments. Forget about organizing by classes, and start organizing by functionality, layers, components, protocols, functional coverage, checking, or anything that you decide is important to you • Easily create flexible code that eases your development burden, and gives your users the power to quickly do what they need to do with your code • Truly create a plug-and-play environment that allows you to add and remove functionality without modifying your code. Examples include how to use AOP to create pluggable debug modules, and a pluggable module that lets you check that your testbench is still working before you begin a regression • Utilize AOP to sidestep those productivity roadblocks that seem to plague all projects at the most inconvenient of times • Discover why “return” is evil, and some other “gotchas” with the AOP features of e All of the methodologies, tips, and techniques described in this book have been developed and tested on real projects, with real people, real schedules and all of the associated problems that come with these. Only the ones that worked, and worked well, have made it in, so by following the advice given in this book, you’ll gain access to the true power of AOP while neatly avoiding the effort of working it all out yourself. • Use AOP to organize your code in a way that makes it easy to deal with the things you really care about in your verification environments. Forget about organizing by classes, and start organizing by functionality, layers, components, protocols, functional coverage, checking, or anything that you decide is important to you • Easily create flexible code that eases your development burden, and gives your users the power to quickly do what they need to do with your code • Truly create a plug-and-play environment that allows you to add and remove functionality without modifying your code. Examples include how to use AOP to create pluggable debug modules, and a pluggable module that lets you check that your testbench is still working before you begin a regression • Utilize AOP to sidestep those productivity roadblocks that seem to plague all projects at the most inconvenient of times • Discover why “return” is evil, and some other “gotchas” with the AOP features of e

mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification.

Based on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill. In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students’ understanding of the material. Other features of this revision include: New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standard Descriptions of UVM features such as factories, the test registry, and the configuration database Expanded code samples and explanations Numerous samples that have been tested on the major SystemVerilog simulators SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.