An Introduction To Logic Circuit Testing

An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References

An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References

An easy to use introduction to the practices and techniques in the field of digital circuit testing. Lala writes in a user-friendly and tutorial style, making the book easy to read, even for the newcomer to fault-tolerant system design. Each informative chapter is self-contained, with little or no previous knowledge of a topic assumed. Extensive references follow each chapter.

The new standard in the field, presenting the latest design and testing methods for logic circuits, and the development of a BASIC-based simulation. Offers designers and test engineers unique coverage of circuit design for testability, stressing the incorporation of hardware into designs that facilitate testing and diagnosis by allowing greater access to internal circuits. Examines various ways of representing a design, as well as external testing methods that apply this information.

This textbook for courses in Digital Systems Design introduces students to the fundamental hardware used in modern computers. Coverage includes both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). Using this textbook enables readers to design digital systems using the modern HDL approach, but they have a broad foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the presentation with learning Goals and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on each outcome.

Your road map for meeting today's digital testing challenges Today, digital logic devices are common in products that impact public safety, including applications in transportation and human implants. Accurate testing has become more critical to reliability, safety, and the bottom line. Yet, as digital systems become more ubiquitous and complex, the challenge of testing them has become more difficult. As one development group designing a RISC stated, "the work required to . . . test a chip of this size approached the amount of effort required to design it." A valued reference for nearly two decades, Digital Logic Testing and Simulation has been significantly revised and updated for designers and test engineers who must meet this challenge. There is no single solution to the testing problem. Organized in an easy-to-follow, sequential format, this Second Edition familiarizes the reader with the many different strategies for testing and their applications, and assesses the strengths and weaknesses of the various approaches. The book reviews the building blocks of a successful testing strategy and guides the reader on choosing the best solution for a particular application. Digital Logic Testing and Simulation, Second Edition covers such key topics as: * Binary Decision Diagrams (BDDs) and cycle-based simulation * Tester architectures/Standard Test Interface Language (STIL) * Practical algorithms written in a Hardware Design Language (HDL) * Fault tolerance * Behavioral Automatic Test Pattern Generation (ATPG) * The development of the Test Design Expert (TDX), the many obstacles encountered and lessons learned in creating this novel testing approach Up-to-date and comprehensive, Digital Logic Testing and Simulation is an important resource for anyone charged with pinpointing faulty products and assuring quality, safety, and profitability.

Today's computers must perform with increasing reliability, which in turn depends onthe problem of determining whether a circuit has been manufactured properly or behaves correctly.However, the greater circuit density of VLSI circuits and systems has made testing more difficultand costly. This book notes that one solution is to develop faster and more efficient algorithms togenerate test patterns or use design techniques to enhance testability - that is, "design fortestability." Design for testability techniques offer one approach toward alleviating this situationby adding enough extra circuitry to a circuit or chip to reduce the complexity of testing. Becausethe cost of hardware is decreasing as the cost of testing rises, there is now a growing interest inthese techniques for VLSI circuits.The first half of the book focuses on the problem of testing:test generation, fault simulation, and complexity of testing. The second half takes up the problemof design for testability: design techniques to minimize test application and/or test generationcost, scan design for sequential logic circuits, compact testing, built-in testing, and variousdesign techniques for testable systems.Hideo Fujiwara is an associate professor in the Department ofElectronics and Communication, Meiji University. Logic Testing and Design for Testability isincluded in the Computer Systems Series, edited by Herb Schwetman.

This textbook introduces readers to the fundamental hardware used in modern computers. The only pre-requisite is algebra, so it can be taken by college freshman or sophomore students or even used in Advanced Placement courses in high school. This book presents both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). This textbook enables readers to design digital systems using the modern HDL approach while ensuring they have a solid foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the content with learning goals and assessment at its core. Each section addresses a specific learning outcome that the learner should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure learner performance on each outcome. This book can be used for either a sequence of two courses consisting of an introduction to logic circuits (Chapters 1-7) followed by logic design (Chapters 8-14) or a single, accelerated course that uses the early chapters as reference material.