Debugging At The Electronic System Level

Debugging becomes more and more the bottleneck to chip design productivity, especially while developing modern complex integrated circuits and systems at the Electronic System Level (ESL). Today, debugging is still an unsystematic and lengthy process. Here, a simple reporting of a failure is not enough, anymore. Rather, it becomes more and more important not only to find many errors early during development but also to provide efficient methods for their isolation. In Debugging at the Electronic System Level the state-of-the-art of modeling and verification of ESL designs is reviewed. There, a particular focus is taken onto SystemC. Then, a reasoning hierarchy is introduced. The hierarchy combines well-known debugging techniques with whole new techniques to improve the verification efficiency at ESL. The proposed systematic debugging approach is supported amongst others by static code analysis, debug patterns, dynamic program slicing, design visualization, property generation, and automatic failure isolation. All techniques were empirically evaluated using real-world industrial designs. Summarized, the introduced approach enables a systematic search for errors in ESL designs. Here, the debugging techniques improve and accelerate error detection, observation, and isolation as well as design understanding.

Electronic System Level Design: an Open-Source Approach is based on the successful experience acquired with the conception of the ADL ArchC, the development of its underlying tool suite, and the building of its platform modeling infrastructure. With more than 10000 accesses per year since 2004, the dissemination of ArchC models reached not only students in quest of proper infrastructure to develop their research projects but also some companies in need of processor models to build virtual platforms using SystemC. The need to anticipate the development of hardware-dependent software and to build virtual prototypes gave rise to Transaction Level Modeling (TLM). Since SystemC provided the elements and the adequate abstraction level for supporting TLM, their relation has grown so strong that OSCI created a TLM Working Group whose effort resulted in the recently released TLM 2.0 standard, which is also covered in this book.

This book describes a set of SystemC‐based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration. Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL). The methodologies discussed enable readers to tackle easily key tasks and applications in the design process.

This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems. It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time. Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today’s multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifying problems and solutions. She then describes out-of-order parallel discrete event simulation (OoO PDES), a novel approach for efficient validation of system-level designs by aggressively exploiting the parallel capabilities of todays’ multi-core PCs. This approach enables readers to design simulators that can fully exploit the parallel processing capability of the multi-core system to achieve fast speed simulation, without loss of simulation and timing accuracy. Based on this parallel simulation infrastructure, the author further describes automatic approaches that help the designer quickly to narrow down the debugging targets in faulty ESL models with parallelism.

Platform Based Design at the Electronic System Level presents a multi-faceted view of the challenges facing the electronic industry in the development and integration of complex heterogeneous systems, including both hardware and software components. It analyses and proposes solutions related to the provision of integration platforms by System on Chip and Integrated Platform providers in light of the needs and requirements expressed by the system companies: they are the users of such platforms, which they apply to develop their next-generation products. This is the first book to examine ESL from perspectives of system developer, platform provider and Electronic Design Automation.

Addressing the need for full and accurate functional information during the design process, this guide offers a comprehensive overview of functional verification from the points of view of leading experts at work in the electronic-design industry.

Modern electronic systems consist of a fairly heterogeneous set of components. Today, a single system can be constituted by a hardware platform, frequently composed of a mix of analog and digital components, and by several software application layers. The hardware can include several heterogeneous microprocessors (e.g. GPP, DSP, GPU, etc.), dedicated ICs (ASICs and/or FPGAs), memories, a set of local connections between the system components, and some interfaces between the system and the environment (sensors, actuators, etc.). Therefore, on the one hand, multi-processor embedded systems are capable of meeting the demand of processing power and flexibility of complex applications. On the other hand, such systems are very complex to design and optimize, so that the design methodology plays a major role in determining the success of the products. For these reasons, to cope with the increasing system complexity, the approaches typically used today are oriented towards co-design methodologies working at the higher levels of abstraction. Unfortunately, such methodologies are typically customized for the specific application, suffer of a lack of generality and still need a considerable effort when real-size project are envisioned. Therefore, there is still the need for a general methodology able to support the designer during the high-level steps of a co-design flow, enabling an effective design space exploration before tackling the low-level steps and thus committing to the final technology. This should prevent costly redesign loops.In such a context, the work described in this book, composed of two parts, aims at providing models, methodologies and tools to support each step of the co-design flow of embedded systems implemented by exploiting heterogeneous multi-processor architectures mapped on distributed systems, as well as fully integrated onto a single chip.

This book describes a flexible and largely automated methodology for adding the estimation of power consumption to high level simulations at the electronic system level (ESL). This method enables the inclusion of power consumption considerations from the very start of a design. This ability can help designers of electronic systems to create devices with low power consumption. The authors also demonstrate the implementation of the method, using the popular ESL language “SystemC”. This implementation enables most existing SystemC ESL simulations for power estimation with very little manual work. Extensive case-studies of a Network on Chip communication architecture and a dual-core application processor “ARM Cortex-A9” showcase the applicability and accuracy of the method to different types of electronic devices. The evaluation compares various trade-offs regarding amount of manual work, types of ESL models, achieved estimation accuracy and impact on the simulation speed. Describes a flexible and largely automated ESL power estimation method; Shows implementation of power estimation methodology in SystemC; Uses two extensive case studies to demonstrate method introduced.