High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications

This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.

One of the main trends of microelectronics is toward design for integrated systems, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). Due to this development, design techniques for mixed-signal circuits become more important than before. Among other devices, analog-to-digital and digital-to-analog converters are the two bridges between the analog and the digital worlds. Besides, low-power design technique is one of the main issues for embedded systems, especially for hand-held applications. Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems aims at design techniques for low-power, high-speed analog-to-digital converter processed by the standard CMOS technology. Additionally this book covers physical integration issues of A/D converter integrated in SoC, i.e., substrate crosstalk and reference voltage network design.

This book covers a variety of topics in Electronics and Communication Engineering, especially in the area of microelectronics and VLSI design, communication systems and networks, and signal and image processing. The content is based on papers presented at the 5th International Conference on VLSI, Communication and Signal Processing (VCAS 2022). The book also discusses the emerging applications of novel tools and techniques in image, video, and multimedia signal processing. This book is useful to students, researchers, and professionals working in the electronics and communication domain.

CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes in depth converter specifications like Effective Number of Bits (ENOB), Spurious Free Dynamic Range (SFDR), Integral Non-Linearity (INL), Differential Non-Linearity (DNL) and sampling clock jitter requirements. Relations between these specifications and practical issues like matching of components and offset parameters of differential pairs are derived. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes the requirements of input and signal reconstruction filtering in case a converter is applied into a signal processing system. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes design details of high-speed A/D and D/A converters, high-resolution A/D and D/A converters, sample-and-hold amplifiers, voltage and current references, noise-shaping converters and sigma-delta converters, technology parameters and matching performance, comparators and limitations of comparators and finally testing of converters.

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.

This book contains the revised contributions of the 18 tutorial speakers at the tenth AACD 2001 in Noordwijk, the Netherlands, April 24-26. The conference was organized by Marcel Pelgrom, Philips Research Eindhoven, and Ed van Tuijl, Philips Research Eindhoven and Twente University, Enschede, the Netherlands. The program committee consisted of: Johan Huijsing, Delft University of Technology Arthur van Roermund, Eindhoven University of Technology Michiel Steyaert, Catholic University of Leuven The program was concentrated around three main topics in analog circuit design. Each of these topics has been covered by six papers. The three main topics are: Scalable Analog Circuit Design High-Speed D/A Converters RF Power Amplifiers Other topics covered before in this series: 2000 High-Speed Analog-to-Digital Converters Mixed Signal Design PLL’s and Synthesizers 1999 XDSL and other Communication Systems RF MOST Models Integrated Filters and Oscillators 1998 1-Volt- Electronics Mixed-Mode Systems Low-Noise and RF Power Amplifiers for Telecommunication vii viii 1997 RF A-D Converters Sensor and Actuator Interfaces Low-Noise Oscillators, PLL’s and Synthesizers 1996 RF CMOS Circuit Design Bandpass Sigma Delta and other Converters Translinear Circuits 1995 Low-Noise, Low-Power, Low-Voltage Mixed Mode with CAD Trials Voltage, Current and Time References 1994 Low-Power Low Voltage Integrated Filters Smart power 1993 Mixed-Mode A/D Design Sensor Interfaces Communications Circuits 1992 Op Amps ADC’s Analog CAD We hope to serve the analog design community with these series of books and plan to continue this series in the future. Johan H.

Artificial intelligence (AI), the internet of things (IoT), and blockchain provide services to 6G in the form of radio resource management, mobility management, energy management, and network management. Moreover, 6G strengthens AI and blockchain-based applications. Further study on the benefits and potential opportunities of 6G for AI and blockchain is required to utilize the technology successfully. Role of 6G Wireless Networks in AI and Blockchain-Based Applications considers the role of the 6G wireless network deployed on AI and blockchain technology-based applications in fields such as the healthcare industry, agriculture, e-business, and transportation. The book specifically focuses on remote healthcare monitoring, online shopping preference, V2V communication, UAV, holographic application, and augmented and virtual reality as advanced services of 6G networks. Covering topics such as machine learning, smart cities, and virtual reality, this reference work is ideal for computer scientists, policymakers, researchers, scholars, academicians, practitioners, instructors, and students.