Low Power Hf Microelectronics

This book brings together innovative modelling, simulation and design techniques in CMOS, SOI, GaAs and BJT to achieve successful high-yield manufacture for low-power, high-speed and reliable-by-design analogue and mixed-mode integrated systems.

The book is organised in four parts, with generous contributions covering: (i) process/TCAD technology; (ii) device modelling/characterisation and circuit simulation; (iii) reliability and testability; (iv) analog and digital circuit and system design. In modern low-power HF microelectronics, the interaction needed between these parts to achieve the desired system performances means that frequently there will be an alliance and/or overlap among them. It is fundamental to high-yield successful manufacturing to relate in a quantitative manner the sensitivity of the electrical performance of the final devices and/or circuits to variations in structural parameters, doping profiles, layout, thermal effects and design

Very Large Scale Integration (VLSI) Systems refer to the latest development in computer microchips which are created by integrating hundreds of thousands of transistors into one chip. Emerging research in this area has the potential to uncover further applications for VSLI technologies in addition to system advancements. Design and Modeling of Low Power VLSI Systems analyzes various traditional and modern low power techniques for integrated circuit design in addition to the limiting factors of existing techniques and methods for optimization. Through a research-based discussion of the technicalities involved in the VLSI hardware development process cycle, this book is a useful resource for researchers, engineers, and graduate-level students in computer science and engineering.

Low Power Design in Deep Submicron Electronics deals with the different aspects of low power design for deep submicron electronics at all levels of abstraction from system level to circuit level and technology. Its objective is to guide industrial and academic engineers and researchers in the selection of methods, technologies and tools and to provide a baseline for further developments. Furthermore the book has been written to serve as a textbook for postgraduate student courses. In order to achieve both goals, it is structured into different chapters each of which addresses a different phase of the design, a particular level of abstraction, a unique design style or technology. These design-related chapters are amended by motivations in Chapter 2, which presents visions both of future low power applications and technology advancements, and by some advanced case studies in Chapter 9. From the Foreword: `... This global nature of design for low power was well understood by Wolfgang Nebel and Jean Mermet when organizing the NATO workshop which is the origin of the book. They invited the best experts in the field to cover all aspects of low power design. As a result the chapters in this book are covering deep-submicron CMOS digital system design for low power in a systematic way from process technology all the way up to software design and embedded software systems. Low Power Design in Deep Submicron Electronics is an excellent guide for the practicing engineer, the researcher and the student interested in this crucial aspect of actual CMOS design. It contains about a thousand references to all aspects of the recent five years of feverish activity in this exciting aspect of design.' Hugo de Man Professor, K.U. Leuven, Belgium Senior Research Fellow, IMEC, Belgium

With a billion – soon to be two billion - cellular telephones in circulation, the next challenge is to make cellular radio functions adaptive to their environment. This book provides a comprehensive theoretical framework for optimizing performance, discussing joint optimization of Noise Figure and Input Intercept Point in receiver systems. Also examined are original techniques to optimize voltage controlled oscillators and low-noise amplifiers, minimizing power consumption while maintaining adequate system performance.

Motivated by consumer demand for smaller, more portable electronic devices that offer more features and operate for longer on their existing battery packs, cutting edge electronic circuits need to be ever more power efficient. For the circuit designer, this requires an understanding of the latest low voltage and low power (LV/LP) techniques, one of the most promising of which makes use of the floating gate MOS (FGMOS) transistor.

Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.

There is arguably no field in greater need of a comprehensive handbook than computer engineering. The unparalleled rate of technological advancement, the explosion of computer applications, and the now-in-progress migration to a wireless world have made it difficult for engineers to keep up with all the developments in specialties outside their own