Low Power High Resolution Analog To Digital Converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.

This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.

One of the main trends of microelectronics is toward design for integrated systems, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). Due to this development, design techniques for mixed-signal circuits become more important than before. Among other devices, analog-to-digital and digital-to-analog converters are the two bridges between the analog and the digital worlds. Besides, low-power design technique is one of the main issues for embedded systems, especially for hand-held applications. Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems aims at design techniques for low-power, high-speed analog-to-digital converter processed by the standard CMOS technology. Additionally this book covers physical integration issues of A/D converter integrated in SoC, i.e., substrate crosstalk and reference voltage network design.

Micro-electronics and so integrated circuit design are heavily driven by technology scaling. The main engine of scaling is an increased system performance at reduced manufacturing cost (per system). In most systems digital circuits dominate with respect to die area and functional complexity. Digital building blocks take full - vantage of reduced device geometries in terms of area, power per functionality, and switching speed. On the other hand, analog circuits rely not on the fast transition speed between a few discrete states but fairly on the actual shape of the trans- tor characteristic. Technology scaling continuously degrades these characteristics with respect to analog performance parameters like output resistance or intrinsic gain. Below the 100 nm technology node the design of analog and mixed-signal circuits becomes perceptibly more dif cult. This is particularly true for low supply voltages near to 1V or below. The result is not only an increased design effort but also a growing power consumption. The area shrinks considerably less than p- dicted by the digital scaling factor. Obviously, both effects are contradictory to the original goal of scaling. However, digital circuits become faster, smaller, and less power hungry. The fast switching transitions reduce the susceptibility to noise, e. g. icker noise in the transistors. There are also a few drawbacks like the generation of power supply noise or the lack of power supply rejection.

This book offers students and those new to the topic of analog-to-digital converters (ADCs) a broad introduction, before going into details of the state-of-the-art design techniques for SAR and DS converters, including the latest research topics, which are valuable for IC design engineers as well as users of ADCs in applications. The book then addresses important topics, such as correct connectivity of ADCs in an application, the verification, characterization and testing of ADCs that ensure high-quality end products. Analog-to-digital converters are the central element in any data processing system and regulation loops such as modems or electrical motor drives. They significantly affect the performance and resolution of a system or end product. System development engineers need to be familiar with the performance parameters of the converters and understand the advantages and disadvantages of the various architectures. Integrated circuit development engineers have to overcome the problem of achieving high performance and resolution with the lowest possible power dissipation, while the digital circuitry generates distortion in supply, ground and substrate. This book explains the connections and gives suggestions for obtaining the highest possible resolution. Novel trends are illustrated in the design of analog-to-digital converters based on successive approximation and the difficulties in the development of continuous-time delta-sigma modulators are also discussed.

Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.

This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.

A number of digital applications e.g. professional cameras, voice communication, video digitizers, data imaging and many more require low power, high speed, and high resolution analog to digital converters. But for high speed data communication systems with increased resolution and high sampling rates, different linear and nonlinear errors of ADCs come in picture which is a big challenge for design engineers to remove.A unique digital background calibration technique, a combination of signal dependent dithering with butterfly shuffler is proposed here for multi-bit, SHA-less 16-bit, 125 MS/s Pipelined ADC. The purpose of the research work was to integrate different stages of different sizes to achieve 16-bit error-free output at high sampling rate by using unique background calibration technique for SHA-less circuit. Because the achieved values of SNDR and SFDR are high with low power consumption, so this proposed ADC is suitable for high resolution applications like video communication. Without using sample and hold amplifier we saved power and reduced noise interference. Additional advantage of SHA removal is to use a smaller input sampling capacitor which increases ADC's drivability. A new timing diagram is also proposed here to resolve the sampling clock skew. The ultimate multi-bit front-end proposed here helped to save further power.The proposed comparator is able to avoid the kickback as compared to traditional comparators. For the initial multi-bit stage, a two-stage gain boosted amplifier is used to achieve high gain and to reduce the nonlinear gain errors. Because the non-idealities of Op-amp and capacitor mismatching errors, the ADC transfer function may achieve erroneous values by DNL errors, so the proposed technique is made capable to remove linear gain and offset errors and capacitor mismatching errors. Also the small signal linearity errors removed with the proposed architecture of 16-bit Pipelined ADC. Along with these advantages, high values of SNDR and SFDR has achieved, which is a top most indicator to distinguish the signal out from other noise and spurious frequencies.