Vlsi And Post Cmos Electronics

VLSI, or Very-Large-Scale-Integration, is the practice of combining billions of transistors to create an integrated circuit. At present, VLSI circuits are realised using CMOS technology. However, the demand for ever smaller, more efficient circuits is now pushing the limits of CMOS. Post-CMOS refers to the possible future digital logic technologies beyond the CMOS scaling limits. This 2-volume set addresses the current state of the art in VLSI technologies and presents potential options for post-CMOS processes. VLSI and Post-CMOS Electronics is a useful reference guide for researchers, engineers and advanced students working in the area of design and modelling of VLSI and post-CMOS devices and their circuits. Volume 1 focuses on design, modelling and simulation, including applications in low voltage and low power VLSI, and post-CMOS devices and circuits. Volume 2 addresses a wide range of devices, circuits and interconnects.

The following topics are dealt with: integrated circuit design; VLSI; technology CAD (electronics); MOSFET; III-V semiconductors; silicon; semiconductor device models; SRAM chips; three-dimensional integrated circuits; permittivity.

VLSI, or Very-Large-Scale-Integration, is the practice of combining billions of transistors to create an integrated circuit. At present, VLSI circuits are realised using CMOS technology. However, the demand for ever smaller, more efficient circuits is now pushing the limits of CMOS. Post-CMOS refers to the possible future digital logic technologies beyond the CMOS scaling limits. This 2-volume set addresses the current state of the art in VLSI technologies and presents potential options for post-CMOS processes. VLSI and Post-CMOS Electronics is a useful reference guide for researchers, engineers and advanced students working in the area of design and modelling of VLSI and post-CMOS devices and their circuits. Volume 1 focuses on design, modelling and simulation, including applications in low voltage and low power VLSI, and post-CMOS devices and circuits. Volume 2 addresses a wide range of devices, circuits and interconnects.

Over two volumes this work describes the modelling, design, and implementation of nano-scaled CMOS electronics, and the new generation of post-CMOS devices, at both the device and circuit levels.

Continuing from volume 1, this volume outlines circuit- and system-level design approaches and issues for these devices. Topics covered include self-healing analog/RF circuits; on-chip gate delay variability measurement in scaled technology; FinFET SRAM circuits; nanoscale FinFET devices for PVT aware SRAM; low leakage variability aware CMOS logic circuits; thermal effects in MWCNT VLSI interconnects; an accurate PVT-aware statistical logic library for nano-CMOS integrated circuits; SPICEless RTL design optimization of nano-electronic digital integrated circuits; power-delay trade-off driven optimal scheduling of CDFGs during high level synthesis; green on-chip inductors for three-dimensional integrated circuits; 3D NoC -- a promising alternative for tomorrow's nano-system design; and DNA computing.

During the last decade, CMOS has become increasingly attractive as a basic integrated circuit technology due to its low power (at moderate frequencies), good scalability, and rail-to-rail operation. There are now a variety of CMOS circuit styles, some based on static complementary con ductance properties, but others borrowing from earlier NMOS techniques and the advantages of using clocking disciplines for precharge-evaluate se quencing. In this comprehensive book, the reader is led systematically through the entire range of CMOS circuit design. Starting with the in dividual MOSFET, basic circuit building blocks are described, leading to a broad view of both combinatorial and sequential circuits. Once these circuits are considered in the light of CMOS process technologies, impor tant topics in circuit performance are considered, including characteristics of interconnect, gate delay, device sizing, and I/O buffering. Basic circuits are then composed to form macro elements such as multipliers, where the reader acquires a unified view of architectural performance through par allelism, and circuit performance through careful attention to circuit-level and layout design optimization. Topics in analog circuit design reflect the growing tendency for both analog and digital circuit forms to be combined on the same chip, and a careful treatment of BiCMOS forms introduces the reader to the combination of both FET and bipolar technologies on the same chip to provide improved performance.