Advanced Verification Techniques

"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks." - Stuart Swan

The Accellera Universal Verification Methodology (UVM) standard is architected to scale, but verification is growing and in more than just the digital design dimension. It is growing in the SoC dimension to include low-power and mixed-signal and the system integration dimension to include multi-language support and acceleration. These items and others all contribute to the quality of the SOC so the Metric-Driven Verification (MDV) methodology is needed to unify it all into a coherent verification plan. This book is for verification engineers and managers familiar with the UVM and the benefits it brings to digital verification but who also need to tackle specialized tasks. It is also written for the SoC project manager that is tasked with building an efficient worldwide team. While the task continues to become more complex, Advanced Verification Topics describes methodologies outside of the Accellera UVM standard, but that build on it, to provide a way for SoC teams to stay productive and profitable.

Professional Verification is a guide to advanced functional verification in the nanometer era. It presents the best practices in functional verification used today and provides insights on how to solve the problems that verification teams face. Professional Verification is based on the experiences of advanced verification teams throughout the industry, along with work done at Cadence Design Systems. Professional Verification presents a complete and detailed Unified Verification Methodology based on the best practices in use today. It also addresses topics important to those doing advanced functional verification, such as assertions, functional coverage, formal verification, and reactive testbenches.

As design complexity in chips and devices continues to rise, so, too, does the demand for functional verification. Principles of Functional Verification is a hands-on, practical text that will help train professionals in the field of engineering on the methodology and approaches to verification. In practice, the architectural intent of a device is necessarily abstract. The implementation process, however, must define the detailed mechanisms to achieve the architectural goals. Based on a decade of experience, Principles of Functional Verification intends to pinpoint the issues, provide strategies to solve the issues, and present practical applications for narrowing the gap between architectural intent and implementation. The book is divided into three parts, each building upon the chapters within the previous part. Part One addresses why functional verification is necessary, its definition and goals. In Part Two, the heart of the methodology and approaches to solving verification issues are examined. Each chapter in this part ends with exercises to apply what was discussed in the chapter. Part Three looks at practical applications, discussing project planning, resource requirements, and costs. Each chapter throughout all three parts will open with Key Objectives, focal points the reader can expect to review in the chapter. * Takes a "holistic" approach to verification issues * Approach is not restricted to one language * Discussed the verification process, not just how to use the verification language

Advanced Formal Verification shows the latest developments in the verification domain from the perspectives of the user and the developer. World leading experts describe the underlying methods of today's verification tools and describe various scenarios from industrial practice. In the first part of the book the core techniques of today's formal verification tools, such as SAT and BDDs are addressed. In addition, multipliers, which are known to be difficult, are studied. The second part gives insight in professional tools and the underlying methodology, such as property checking and assertion based verification. Finally, analog components have to be considered to cope with complete system on chip designs.

This book constitutes the refereed proceedings of the 9th International Haifa Verification Conference, HVC 2013, held in Haifa, Israel in November 2013. The 24 revised full papers presented were carefully reviewed and selected from 49 submissions. The papers are organized in topical sections on SAT and SMT-based verification, software testing, supporting dynamic verification, specification and coverage, abstraction and model presentation.

This book constitutes the refereed proceedings of the 24th International Conference on Computer Aided Verification, CAV 2012, held in Berkeley, CA, USA in July 2012. The 38 regular and 20 tool papers presented were carefully reviewed and selected from 185 submissions. The papers are organized in topical sections on automata and synthesis, inductive inference and termination, abstraction, concurrency and software verification, biology and probabilistic systems, embedded and control systems, SAT/SMT solving and SMT-based verification, timed and hybrid systems, hardware verification, security, verification and synthesis, and tool demonstration.

It is a pleasure to present the proceedings of the 22nd European Conference on Object-Oriented Programming (ECOOP 2008) held in Paphos, Cyprus. The conference continues to serve a broad object-oriented community with a tech- cal program spanning theory and practice and a healthy mix of industrial and academic participants. This year a strong workshop and tutorial program c- plementedthemaintechnicaltrack.Wehad13workshopsand8tutorials,aswell as the co-located Dynamic Language Symposium (DLS). Finally, the program was rounded out with a keynote by Rachid Guerraoui and a banquet speech by James Noble. As in previous years, two Dahl-Nygaard awards were selected by AITO, and for the ?rst time, the ECOOP Program Committee gave a best paper award. Theproceedingsinclude27papersselectedfrom138submissions.Thepapers werereviewed in a single-blind process with three to ?ve reviews per paper. P- liminaryversionsofthereviewsweremadeavailabletotheauthorsaweekbefore the PC meeting to allow for short (500 words or less) author responses. The - sponses were discussed at the PC meeting and were instrumental in reaching decisions. The PC discussions followed Oscar Nierstrasz’Champion pattern. PC papers had ?ve reviews and were held at a higher standard.