Advances In Analog And Rf Ic Design For Wireless Communication Systems

The recent and dramatic increase in demand for mobile data communication, driven by consumer devices such as smartphones and tablets, is resulting in heightened technical challenges for the wireless infrastructure that lies as a bridge in-between these mobile terminals and the wired network transferring the data between final users. Several challenges arise in the design of the electronics behind the wireless infrastructure access points, or base-stations. This Chapter provides an overview of the present state, challenges and trends in the RF, analog and mixed signal electronics for wireless infrastructure and provides a frame to orient the reader of this book to the following chapters covering the specifics of the technologies involved.

This chapter provides an overview of design techniques and system aspects relevant to the application of high-speed pipelined ADCs in wireless base transceiver stations (BTS). The discussion begins with a derivation of typical ADC specifications for the receive path of a multi-carrier BTS system. Next, we investigate issues pertaining to the interface between the ADC and its driving circuitry, including complications that arise with sample-and-hold-amplifier-less (SHA-less) ADC frontends. Lastly, we summarize recent research results that look into the digital linearization of dynamic nonlinearities at the ADC’s frontend.

In less than one decade after their introduction into radio-frequency applications, digital fractional-N phase-locked loops (PLLs) have become a relevant topic in microelectronic research and a practical solution for products. In addition to the well-known advantages, such as their silicon area occupation scaling as technology node and their easier portability to new nodes, digital PLLs enable easy and low-cost implementation of calibration techniques, which substantially reduce spurious tones and remove other major analog impairments. In wideband PLLs, the ultimate level of spur performance is often bounded by the time resolution and the linearity of the time-to-digital converter within the digital PLL. Methods for mitigating its nonlinearity such as those based on element randomization and large-scale dithering are discussed. The use of fractional-N dividers based on digital-to-time converters, as a means to relax the design of the time-to-digital converter, is also reviewed. This concept is extended to the limit case of a single-bit time-to-digital converter, which provides best PLL noise–power trade-off with good spur performance.

This chapter offers a system-level analysis of advanced RF transceivers intended for use in wireless and particularly mobile applications. An overview of RF cellular standards is presented, followed by a discussion of various radio architectures. The key radio requirements are derived, and translated to circuit specs, giving an overview of a practical top-down radio design. Several radio non-idealities resulting from RF CMOS shortcomings are discussed, and various architectural and calibration techniques are introduced to overcome those. We will also cover more advanced topics such as handset calibration, the evolution to broadband, RF diversity, and next-generation mobile standards and their requirements.

This chapter presents high-efficiency power amplifiers (PAs) for wireless infrastructure. It starts by stating the importance of high efficiency and the historical evolution in base station PA concepts. It then introduces the current solution, the Doherty PA. After explaining the fundamentals of the Doherty PA, a novel implementation achieving more than 35% drain efficiency across a 6dB power back-off range and up to 20W peak power between 1.7 and 2.3GHz is given. Afterwards, a future PA concept, switch-mode outphasing PA, is introduced. Theory and implementation details of a class-E outphasing PA achieving more than 60% drain efficiency across a 6dB power back-off range and up to 19W peak power between 1800 and 2050MHz is explained. By the end of the chapter, an essential part of switch-mode PAs, high voltage (up to 10V) and high frequency (up to 4GHz) drivers are presented.

This chapter presents one of the first integrated Ku-band downconverters with PLL frequency synthesizer that has widely penetrated the market of low noise blocks (LNBs) for reception of satellite television. It starts with a brief description of the general architecture of a LNB and a presentation of the main requirements for the integrated downconverter and frequency synthesizer. The architecture of the integrated circuit and the design of its building blocks are then presented and discussed in detail. The emphasis is put on the design choices made in the downconverter and the synthesizer for competing in cost and performance with discrete implementations at minimal power consumption. By the end of the chapter, measurement results are reported that illustrate the downconverter performance alone or within a demonstration LNB.

This paper reviews recent developments of interleaved Successive Approximation Analog-to-Digital converters (SAR) in deep sub-micron CMOS technologies. The discussion covers design tradeoffs and degrees of freedom related to the impact of extensive interleaving with many SAR units on bandwidth, noise, linearity, and spurious performance. The impact of interleaving mismatches on representative broadband and multi-carrier narrowband signals is also discussed. Next, two examples are given demonstrating how interleaving with many ADCs can be transformed from a weakness to a strength. The first example concerns low spurious performance enabled by redundant SAR converters and randomization of their operation. The second example presents spectral sensing techniques.

Advances in Analog and RF IC Design for Wireless Communication Systems gives technical introductions to the latest and most significant topics in the area of circuit design of analog/RF ICs for wireless communication systems, emphasizing wireless infrastructure rather than handsets. The book ranges from very high performance circuits for complex wireless infrastructure systems to selected highly integrated systems for handsets and mobile devices. Coverage includes power amplifiers, low-noise amplifiers, modulators, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), and even single-chip radios. This book offers a quick grasp of emerging research topics in RF integrated circuit design and their potential applications, with brief introductions to key topics followed by references to specialist papers for further reading. All of the chapters, compiled by editors well known in their field, have been authored by renowned experts in the subject. Each includes a complete introduction, followed by the relevant most significant and recent results on the topic at hand. This book gives researchers in industry and universities a quick grasp of the most important developments in analog and RF integrated circuit design. Emerging research topics in RF IC design and its potential application Case studies and practical implementation examples Covers fundamental building blocks of a cellular base station system and satellite infrastructure Insights from the experts on the design and the technology trade-offs, the challenges and open questions they often face References to specialist papers for further reading