Low Power Variation Tolerant Design In Nanometer Silicon

Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.

This book provides readers with an overview of the architectures, programming frameworks, and hardware accelerators for typical cloud computing applications in data centers. The authors present the most recent and promising solutions, using hardware accelerators to provide high throughput, reduced latency and higher energy efficiency compared to current servers based on commodity processors. Readers will benefit from state-of-the-art information regarding application requirements in contemporary data centers, computational complexity of typical tasks in cloud computing, and a programming framework for the efficient utilization of the hardware accelerators.

This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level “design hints” are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.

This book constitutes the refereed proceedings of the 22st International Symposium on VLSI Design and Test, VDAT 2018, held in Madurai, India, in June 2018. The 39 full papers and 11 short papers presented together with 8 poster papers were carefully reviewed and selected from 231 submissions. The papers are organized in topical sections named: digital design; analog and mixed signal design; hardware security; micro bio-fluidics; VLSI testing; analog circuits and devices; network-on-chip; memory; quantum computing and NoC; sensors and interfaces.

CMOS Test and Evaluation: A Physical Perspective is a single source for an integrated view of test and data analysis methodology for CMOS products, covering circuit sensitivities to MOSFET characteristics, impact of silicon technology process variability, applications of embedded test structures and sensors, product yield, and reliability over the lifetime of the product. This book also covers statistical data analysis and visualization techniques, test equipment and CMOS product specifications, and examines product behavior over its full voltage, temperature and frequency range.

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

This book constitutes the refereed proceedings of the 26th International Conference on Architecture of Computing Systems, ARCS 2013, held in Prague, Czech Republic, in February 2013. The 29 papers presented were carefully reviewed and selected from 73 submissions. The topics covered are computer architecture topics such as multi-cores, memory systems, and parallel computing, adaptive system architectures such as reconfigurable systems in hardware and software, customization and application specific accelerators in heterogeneous architectures, organic and autonomic computing including both theoretical and practical results on self-organization, self-configuration, self-optimization, self-healing, and self-protection techniques, operating systems including but not limited to scheduling, memory management, power management, RTOS, energy-awareness, and green computing.