Open Verification Methodology Cookbook

Functional verification is an art as much as a science. It requires not only creativity and cunning, but also a clear methodology to approach the problem. The Open Verification Methodology (OVM) is a leading-edge methodology for verifying designs at multiple levels of abstraction. It brings together ideas from electrical, systems, and software engineering to provide a complete methodology for verifying large scale System-on-Chip (SoC) designs. OVM defines an approach for developing testbench architectures so they are modular, configurable, and reusable. This book is designed to help both novice and experienced verification engineers master the OVM through extensive examples. It describes basic verification principles and explains the essentials of transaction-level modeling (TLM). It leads readers from a simple connection of a producer and a consumer through complete self-checking testbenches. It explains construction techniques for building configurable, reusable testbench components and how to use TLM to communicate between them. Elements such as agents and sequences are explained in detail.

This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric. Two implementations of the simulation-only layer are included: Extended Re Channel is a System C library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification.

This book constitutes the refereed proceedings of the 9th International Haifa Verification Conference, HVC 2013, held in Haifa, Israel in November 2013. The 24 revised full papers presented were carefully reviewed and selected from 49 submissions. The papers are organized in topical sections on SAT and SMT-based verification, software testing, supporting dynamic verification, specification and coverage, abstraction and model presentation.

A guide to applying software design principles and coding practices to VHDL to improve the readability, maintainability, and quality of VHDL code. This book addresses an often-neglected aspect of the creation of VHDL designs. A VHDL description is also source code, and VHDL designers can use the best practices of software development to write high-quality code and to organize it in a design. This book presents this unique set of skills, teaching VHDL designers of all experience levels how to apply the best design principles and coding practices from the software world to the world of hardware. The concepts introduced here will help readers write code that is easier to understand and more likely to be correct, with improved readability, maintainability, and overall quality. After a brief review of VHDL, the book presents fundamental design principles for writing code, discussing such topics as design, quality, architecture, modularity, abstraction, and hierarchy. Building on these concepts, the book then introduces and provides recommendations for each basic element of VHDL code, including statements, design units, types, data objects, and subprograms. The book covers naming data objects and functions, commenting the source code, and visually presenting the code on the screen. All recommendations are supported by detailed rationales. Finally, the book explores two uses of VHDL: synthesis and testbenches. It examines the key characteristics of code intended for synthesis (distinguishing it from code meant for simulation) and then demonstrates the design and implementation of testbenches with a series of examples that verify different kinds of models, including combinational, sequential, and FSM code. Examples from the book are also available on a companion website, enabling the reader to experiment with the complete source code.

To realize the full potential of micro- and nanoscale devices in system building, it is critical to develop systems engineering methodologies that successfully integrate stand-alone, small-scale technologies that can effectively interface with the macro world. So how do we accomplish this?Systems Engineering for Microscale and Nanoscale Technologie

This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader System Verilog language, demonstrating the ways that assertions can interact with other System Verilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012. System Verilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.

This book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs. Provides comprehensive coverage of the entire IEEE standard SystemVerilog language; Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features; Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online; Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs. This is quite a comprehensive work. It must have taken a long time to write it. I really like that the author has taken apart each of the SystemVerilog constructs and talks about them in great detail, including example code and simulation logs. For example, there is a chapter dedicated to arrays, and another dedicated to queues - that is great to have! The Language Reference Manual (LRM) is quite dense and difficult to use as a text for learning the language. This book explains semantics at a level of detail that is not possible in an LRM. This is the strength of the book. This will be an excellent book for novice users and as a handy reference for experienced programmers. Mark Glasser Cerebras Systems

This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP. This is the first book published on this subject.