Plasma Etching

The focus of this book is the remarkable advances in understanding of low pressure RF (radio frequency) glow discharges. A basic analytical theory and plasma physics are explained. Plasma diagnostics are also covered before the practicalities of etcher use are explored.

This book has been written as part of a series of scientific books being published by Plenum Press. The scope of the series is to review a chosen topic in each volume. To supplement this information, the abstracts to the most important references cited in the text are reprinted, thus allowing the reader to find in-depth material without having to refer to many additional publications. This volume is dedicated to the field of dry (plasma) etching, as applied in silicon semiconductor processing. Although a number of books have appeared dealing with this area of physics and chemistry, these all deal with parts of the field. This book is unique in that it gives a compact, yet complete, in-depth overview of fundamentals, systems, processes, tools, and applications of etching with gas plasmas for VLSI. Examples are given throughout the fundamental sections, in order to give the reader a better insight in the meaning and magnitude of the many parameters relevant to dry etching. Electrical engineering concepts are emphasized to explain the pros and cons of reactor concepts and excitation frequency ranges. In the description of practical applications, extensive use is made of cross-referencing between processes and materials, as well as theory and practice. It is thus intended to provide a total model for understanding dry etching. The book has been written such that no previous knowledge of the subject is required. It is intended as a review of all aspects of dry etching for silicon semiconductor processing.

Plasma etching has long enabled the perpetuation of Moore's Law. Today, etch compensation helps to create devices that are smaller than 20 nm. But, with the constant downscaling in device dimensions and the emergence of complex 3D structures (like FinFet, Nanowire and stacked nanowire at longer term) and sub 20 nm devices, plasma etching requirements have become more and more stringent. Now more than ever, plasma etch technology is used to push the limits of semiconductor device fabrication into the nanoelectronics age. This will require improvement in plasma technology (plasma sources, chamber design, etc.), new chemistries (etch gases, flows, interactions with substrates, etc.) as well as a compatibility with new patterning techniques such as multiple patterning, EUV lithography, Direct Self Assembly, ebeam lithography or nanoimprint lithography. This book presents these etch challenges and associated solutions encountered throughout the years for transistor realization. Helps readers discover the master technology used to pattern complex structures involving various materials Explores the capabilities of cold plasmas to generate well controlled etched profiles and high etch selectivities between materials Teaches users how etch compensation helps to create devices that are smaller than 20 nm

This is the first of two books presenting the challenges and future prospects of plasma etching processes for microelectronics, reviewing the past, present and future issues of etching processes in order to improve the understanding of these issues through innovative solutions. This book focuses on back end of line (BEOL) for high performance device realization and presents an overview of all etch challenges for interconnect realization as well as the current etch solutions proposed in the semiconductor industry. The choice of copper/low-k interconnect architecture is one of the keys for integrated circuit performance, process manufacturability and scalability. Today, implementation of porous low-k material is mandatory in order to minimize signal propagation delay in interconnections. In this context, the traditional plasma process issues (plasma-induced damage, dimension and profile control, selectivity) and new emerging challenges (residue formation, dielectric wiggling) are critical points of research in order to control the reliability and reduce defects in interconnects. These issues and potential solutions are illustrated by the authors through different process architectures available in the semiconductor industry (metallic or organic hard mask strategies). Presents the difficulties encountered for interconnect realization in very large-scale integrated (VLSI) circuits Focused on plasma-dielectric surface interaction Helps you further reduce the dielectric constant for the future technological nodes

This volume collects together for the first time a series of in-depth, critical reviews of important topics in dry etching, such as dry processing of III-V compound semiconductors, dry etching of refractory metal silicides and dry etching aluminium and aluminium alloys. This topical format provides the reader with more specialised information and references than found in a general review article. In addition, it presents a broad perspective which would otherwise have to be gained by reading a large number of individual research papers. An additional important and unique feature of this book is the inclusion of an extensive literature review of dry processing, compiled by search of computerized data bases. A subject index allows ready access to the key points raised in each of the chapters.

This book is a must-have reference to dry etching technology for semiconductors, which will enable engineers to develop new etching processes for further miniaturization and integration of semiconductor integrated circuits. The author describes the device manufacturing flow, and explains in which part of the flow dry etching is actually used. The content is designed as a practical guide for engineers working at chip makers, equipment suppliers and materials suppliers, and university students studying plasma, focusing on the topics they need most, such as detailed etching processes for each material (Si, SiO2, Metal etc) used in semiconductor devices, etching equipment used in manufacturing fabs, explanation of why a particular plasma source and gas chemistry are used for the etching of each material, and how to develop etching processes. The latest, key technologies are also described, such as 3D IC Etching, Dual Damascene Etching, Low-k Etching, Hi-k/Metal Gate Etching, FinFET Etching, Double Patterning etc.