Relaxation Techniques For The Simulation Of Vlsi Circuits

Circuit simulation has been a topic of great interest to the integrated circuit design community for many years. It is a difficult, and interesting, problem be cause circuit simulators are very heavily used, consuming thousands of computer hours every year, and therefore the algorithms must be very efficient. In addi tion, circuit simulators are heavily relied upon, with millions of dollars being gambled on their accuracy, and therefore the algorithms must be very robust. At the University of California, Berkeley, a great deal of research has been devoted to the study of both the numerical properties and the efficient imple mentation of circuit simulation algorithms. Research efforts have led to several programs, starting with CANCER in the 1960's and the enormously successful SPICE program in the early 1970's, to MOTIS-C, SPLICE, and RELAX in the late 1970's, and finally to SPLICE2 and RELAX2 in the 1980's. Our primary goal in writing this book was to present some of the results of our current research on the application of relaxation algorithms to circuit simu lation. As we began, we realized that a large body of mathematical and exper imental results had been amassed over the past twenty years by graduate students, professors, and industry researchers working on circuit simulation. It became a secondary goal to try to find an organization of this mass of material that was mathematically rigorous, had practical relevance, and still retained the natural intuitive simplicity of the circuit simulation subject.

Circuit simulation has been a topic of great interest to the integrated circuit design community for many years. It is a difficult, and interesting, problem be cause circuit simulators are very heavily used, consuming thousands of computer hours every year, and therefore the algorithms must be very efficient. In addi tion, circuit simulators are heavily relied upon, with millions of dollars being gambled on their accuracy, and therefore the algorithms must be very robust. At the University of California, Berkeley, a great deal of research has been devoted to the study of both the numerical properties and the efficient imple mentation of circuit simulation algorithms. Research efforts have led to several programs, starting with CANCER in the 1960's and the enormously successful SPICE program in the early 1970's, to MOTIS-C, SPLICE, and RELAX in the late 1970's, and finally to SPLICE2 and RELAX2 in the 1980's. Our primary goal in writing this book was to present some of the results of our current research on the application of relaxation algorithms to circuit simu lation. As we began, we realized that a large body of mathematical and exper imental results had been amassed over the past twenty years by graduate students, professors, and industry researchers working on circuit simulation. It became a secondary goal to try to find an organization of this mass of material that was mathematically rigorous, had practical relevance, and still retained the natural intuitive simplicity of the circuit simulation subject.

Circuit Simulation Methods and Algorithms provides a step-by-step theoretical consideration of methods, techniques, and algorithms in an easy-to-understand format. Many illustrations explain more difficult problems and present instructive circuits. The book works on three levels: The simulator-user level for practitioners and students who want to better understand circuit simulators. The basic theoretical level, with examples, dedicated to students and beginning researchers. The thorough level for deep insight into circuit simulation based on computer experiments using PSPICE and OPTIMA. Only basic mathematical knowledge, such as matrix algebra, derivatives, and integrals, is presumed.

Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.

Metal Oxide Semiconductor (MOS) transistors are the basic building block ofMOS integrated circuits (I C). Very Large Scale Integrated (VLSI) circuits using MOS technology have emerged as the dominant technology in the semiconductor industry. Over the past decade, the complexity of MOS IC's has increased at an astonishing rate. This is realized mainly through the reduction of MOS transistor dimensions in addition to the improvements in processing. Today VLSI circuits with over 3 million transistors on a chip, with effective or electrical channel lengths of 0. 5 microns, are in volume production. Designing such complex chips is virtually impossible without simulation tools which help to predict circuit behavior before actual circuits are fabricated. However, the utility of simulators as a tool for the design and analysis of circuits depends on the adequacy of the device models used in the simulator. This problem is further aggravated by the technology trend towards smaller and smaller device dimensions which increases the complexity of the models. There is extensive literature available on modeling these short channel devices. However, there is a lot of confusion too. Often it is not clear what model to use and which model parameter values are important and how to determine them. After working over 15 years in the field of semiconductor device modeling, I have felt the need for a book which can fill the gap between the theory and the practice of MOS transistor modeling. This book is an attempt in that direction.

This volume documents the research carried out by visiting scientists attached to the Institute for Mathematical Sciences (IMS) at the National University of Singapore and the Institute of High Performance Computing (IHPC) under the program “Advances and Mathematical Issues in Large Scale Simulation.” From 2002 to 2003, researchers from various countries gathered to initiate interesting and innovative work on various themes related to multiscale simulation and fast algorithms. Today, modeling and simulation are used extensively to solve complex problems and to reduce the use of experimentation during the design and analysis stage. It is important to know the various issues that have to be considered in the successful development of computational methodologies for such work. This volume is a compilation of the research by various visiting scientists in the area of modeling and multiscale simulation. Each article covers a major project and documents how computational methodology, mathematical modeling, high performance computing and simulation are combined in a multiscale scheme to solve a variety of complex problems. Some of these include the design, synthesis, processing, characterization and manufacture of nanomaterials and nanostructures, new algorithms for computational work, and grid computing. Through the included examples, readers can realize the vast potential of computational modeling and large scale simulation for the solution of problems in a variety of disciplines and applications. Contents:Methods of Multiscale Modeling in Mechanics (W A Curtin)Efficient and Accurate Boundary Methods for Computational Optics (C Hafner & J Smajic)Finite Element Modeling of Periodic Structures (Z Lou & J-M Jin)Factorization of Potential and Field Distributions without Utilizing the Addition Theorem (A-R Baghi-Wadji & E Li)Virtualization-Aware Application Framework for Hierarchical Multiscale Simulations on a Grid (A Nakano et al.)Molecular Dynamics Simulation and Local Quantities (T Ikeshoji)Recent Advances in Modeling and Simulation of High-Speed Interconnects (M Nakhla & R Achar)Multiscale Modeling of Degradation and Failure of Interconnect Lines Driven by Electromigration and Stress Gradients (R Atkinson & A M Cuitiño) Readership: Engineers, scientists and graduate students who need further insights into the applications and power of computational methodology for the solution of a wide array of problems. Keywords:Large Scale Simulation;High Performance Computing;Multiscale Simulation;Fast Algorithms;Computational MethodologyKey Features:Provides insight into the applications and power of computational methodology in solving a wide array of complex problems

Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.

A modern microelectronic circuit can be compared to a large construction, a large city, on a very small area. A memory chip, a DRAM, may have up to 64 million bit locations on a surface of a few square centimeters. Each new generation of integrated circuit- generations are measured by factors of four in overall complexity -requires a substantial increase in density from the current technology, added precision, a decrease of the size of geometric features, and an increase in the total usable surface. The microelectronic industry has set the trend. Ultra large funds have been invested in the construction of new plants to produce the ultra large-scale circuits with utmost precision under the most severe conditions. The decrease in feature size to submicrons -0.7 micron is quickly becoming availabl- does not only bring technological problems. New design problems arise as well. The elements from which microelectronic circuits are build, transistors and interconnects, have different shape and behave differently than before. Phenomena that could be neglected in a four micron technology, such as the non-uniformity of the doping profile in a transistor, or the mutual capacitance between two wires, now play an important role in circuit design. This situation does not make the life of the electronic designer easier: he has to take many more parasitic effects into account, up to the point that his ideal design will not function as originally planned.