Advanced Gate Stack Source Drain And Channel Engineering For Si Based Cmos 6 New Materials Processes And Equipment

These proceedings describe processing, materials and equipment for CMOS front-end integration including gate stack, source/drain and channel engineering. Topics: strained Si/SiGe and Si/SiGe on insulator; high-mobility channels including III-V¿s, etc.; nanowires and carbon nanotubes; high-k dielectrics, metal and FUSI gate electrodes; doping/annealing for ultra-shallow junctions; low-resistivity contacts; advanced deposition (e.g. ALD, CVD, MBE), RTP, UV, plasma and laser-assisted processes.

This issue describes processing, materials and equipment for CMOS front-end integration including gate stack, source/drain and channel engineering. Topics: strained Si/SiGe and Si/SiGe on insulator; high-mobility channels including III-V¿s, etc.; nanowires and carbon nanotubes; high-k dielectrics, metal and FUSI gate electrodes; doping/annealing for ultra-shallow junctions; low-resistivity contacts; advanced deposition (e.g. ALD, CVD, MBE), RTP, UV, plasma and laser-assisted processes.

These proceedings describe processing, materials, and equipment for CMOS front-end integration including gate stack, source/drain and channel engineering. Topics: strained Si/SiGe and Si/SiGe on insulator; high-mobility channels including III-V¿s, etc.; nanowires and carbon nanotubes; high-k dielectrics, metal and FUSI gate electrodes; doping/annealing for ultra-shallow junctions; low-resistivity contacts; advanced deposition (e.g. ALD, CVD, MBE), RTP, UV, plasma and laser-assisted processes.

This issue of ¿ECS Transactions¿ describes processing, materials and equipment for CMOS front-end integration including gate stack, source/drain and channel engineering. Topics include strained Si/SiGe and Si/SiGe on insulator; high-mobility channels including III-V¿s, etc.; nanowires and carbon nanotubes; high-k dielectrics, metal and FUSI gate electrodes; doping/annealing for ultra-shallow junctions; low-resistivity contacts; advanced deposition (e.g. ALD, CVD, MBE), RTP, UV, plasma and laser-assisted processes.

This issue of ECS Transactions contains papers presented at the International Symposium on Plasma Processing. The symposium, 17th in the series, cosponsored by the Dielectric Science & Technology, Electronics, and Photonics Divisions was held as part of the 213th Meeting of The Electrochemical Society, Inc., in Phoenix, AZ, USA, May 18 - 23, 2008. A total of 14 papers were presented from Belgium, Germany, Italy, Japan, Republic of Korea, Russia, and the USA on topics mainly focused on diagnostics & measurements and etching & deposition processes.

This issue covers, in detail, all aspects of the physics and the technology of high dielectric constant gate stacks, including high mobility substrates, high dielectric constant materials, processing, metals for gate electrodes, interfaces, physical, chemical, and electrical characterization, gate stack reliability, and DRAM and non-volatile memories.

The papers included in this issue of ECS Transactions were originally presented in the symposium ¿Solid-State Topics General Session¿, held during the PRiME 2008 joint international meeting of The Electrochemical Society and The Electrochemical Society of Japan, with the technical cosponsorship of the Japan Society of Applied Physics, the Korean Electrochemical Society, the Electrochemistry Division of the Royal Australian Chemical Institute, and the Chinese Society of Electrochemistry. This meeting was held in Honolulu, Hawaii, from October 12 to 17, 2008.