Advanced Hardware Design For Error Correcting Codes

This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.

Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation. The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.

This new edition has been extensively revised to reflect the progress in error control coding over the past few years. Over 60% of the material has been completely reworked, and 30% of the material is original. Convolutional, turbo, and low density parity-check (LDPC) coding and polar codes in a unified framework Advanced research-related developments such as spatial coupling A focus on algorithmic and implementation aspects of error control coding

A new class of provably capacity achieving error-correction codes, polar codes are suitable for many problems, such as lossless and lossy source coding, problems with side information, multiple access channel, etc. The first comprehensive book on the implementation of decoders for polar codes, the authors take a tutorial approach to explain the practical decoder implementation challenges and trade-offs in either software or hardware. They also demonstrate new trade-offs in latency, throughput, and complexity in software implementations for high-performance computing and GPGPUs, and hardware implementations using custom processing elements, full-custom application-specific integrated circuits (ASICs), and field-programmable-gate arrays (FPGAs). Presenting a good overview of this research area and future directions, High-Speed Decoders for Polar Codes is perfect for any researcher or SDR practitioner looking into implementing efficient decoders for polar codes, as well as students and professors in a modern error correction class. As polar codes have been accepted to protect the control channel in the next-generation mobile communication standard (5G) developed by the 3GPP, the audience includes engineers who will have to implement decoders for such codes and hardware engineers designing the backbone of communication networks.

Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation. The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.

This IBM® RedpaperTM publication is a comprehensive guide that covers the IBM Power SystemTM E850C (8408-44E) server that supports IBM AIX®, and Linux operating systems. The objective of this paper is to introduce the major innovative Power E850C offerings and their relevant functions. The Power E850C server (8408-44E) is the latest enhancement to the Power Systems portfolio. It offers an improved 4-socket 4U system that delivers faster IBM POWER8® processors up to 4.22 GHz, with up to 4 TB of DDR4 memory, built-in IBM PowerVM® virtualization, and capacity on demand. It also integrates cloud management to help clients deploy scalable, mission-critical business applications in virtualized, private cloud infrastructures. Like its predecessor Power E850 server, which was launched in 2015, the new Power E850C server uses 8-core, 10-core, or 12-core POWER8 processor modules. However, the Power E850C cores are 13%-20% faster and deliver a system with up to 32 cores at 4.22 GHz, up to 40 cores at 3.95 GHz, or up to 48 cores at 3.65 GHz, and use DDR4 memory. A minimum of two processor modules must be installed in each system, with a minimum quantity of one processor module's cores activated. Cloud computing, in its many forms (public, private, or hybrid), is quickly becoming both the delivery and consumption models for IT. However, finding the correct mix between traditional IT, private cloud, and public cloud can be a challenge. The new Power E850C server and IBM Cloud PowerVC manager can enable clients to accelerate the transformation of their IT infrastructure for cloud while providing tremendous flexibility during the transition. IBM Cloud PowerVC Manager provides OpenStack-based cloud management to accelerate and simplify cloud deployment by providing fast and automated VM deployments, prebuilt image templates, and self-service capabilities all with an intuitive interface. PowerVC management upwardly integrates into various third-party hybrid cloud orchestration products, including IBM Cloud Orchestrator, VMware vRealize, and others. Clients can simply manage both their private cloud VMs and their public cloud VMs from a single, integrated management tool. IBM Power Systems is designed to provide the highest levels of reliability, availability, flexibility, and performance to bring you a world-class enterprise private and hybrid cloud infrastructure. Through enterprise-class security, efficient built-in virtualization that drives industry-leading workload density, and dynamic resource allocation and management, the server consistently delivers the highest levels of service across hundreds of virtual workloads on a single system. The Power E850C server includes the cloud management software and services to assist with clients' move to the cloud, both private and hybrid. Those additional capabilities include the following items: Private cloud management with IBM Cloud PowerVC Manager, Cloud-based HMC Apps as a service, and Open source cloud automation and configuration tooling for AIX Hybrid cloud support Hybrid infrastructure management tools Securely connect system of record workloads and data to cloud native applications IBM Cloud Starter Pack Flexible capacity on demand Power to Cloud Services This publication is for professionals who want to acquire a better understanding of IBM Power SystemsTM products. The intended audience includes the following roles: Clients Sales and marketing professionals Technical support professionals IBM Business Partners Independent software vendors This paper expands the current set of IBM Power Systems documentation by providing a desktop reference that offers a detailed technical description of the Power E850C system.

This IBM® RedpaperTM publication is a comprehensive guide covering the IBM Power System E850 (8408-E8E) server that supports IBM AIX®, and Linux operating systems. The objective of this paper is to introduce the major innovative Power E850 offerings and their relevant functions: The new IBM POWER8TM processor, available at frequencies of 3.02 GHz, 3.35 GHz, and 3.72 GHz Significantly strengthened cores and larger caches Two integrated memory controllers with improved latency and bandwidth Integrated I/O subsystem and hot-pluggable PCIe Gen3 I/O slots I/O drawer expansion options offer greater flexibility Improved reliability, serviceability, and availability (RAS) functions IBM EnergyScaleTM technology that provides features such as power trending, power-saving, capping of power, and thermal measurement This publication is for professionals who want to acquire a better understanding of IBM Power SystemsTM products. The intended audience includes the following roles: Clients Sales and marketing professionals Technical support professionals IBM Business Partners Independent software vendors This paper expands the current set of IBM Power Systems documentation by providing a desktop reference that offers a detailed technical description of the Power E850 system. This paper does not replace the latest marketing materials and configuration tools. It is intended as an additional source of information that, together with existing sources, can be used to enhance your knowledge of IBM server solutions.