Copper Interconnects New Contact Metallurgies Structures And Low K Interlevel Dielectrics

The papers included in this issue of ECS Transactions were originally presented in the symposium ¿Low k Inter-Level Metal Dielectrics and New Contact and Barrier Metallurgies/Structures¿, held during the PRiME 2008 joint international meeting of The Electrochemical Society and The Electrochemical Society of Japan, with the technical cosponsorship of the Japan Society of Applied Physics, the Korean Electrochemical Society, the Electrochemistry Division of the Royal Australian Chemical Institute, and the Chinese Society of Electrochemistry. This meeting was held in Honolulu, Hawaii, from October 12 to 17, 2008.

Since overall circuit performance has depended primarily on transistor properties, previous efforts to enhance circuit and system speed were focused on transistors as well. During the last decade, however, the parasitic resistance, capacitance, and inductance associated with interconnections began to influence circuit performance and will be the primary factors in the evolution of nanoscale ULSI technology. Because metallic conductivity and resistance to electromigration of bulk copper (Cu) are better than aluminum, use of copper and low-k materials is now prevalent in the international microelectronics industry. As the feature size of the Cu-lines forming interconnects is scaled, resistivity of the lines increases. At the same time electromigration and stress-induced voids due to increased current density become significant reliability issues. Although copper/low-k technology has become fairly mature, there is no single book available on the promise and challenges of these next-generation technologies. In this book, a leader in the field describes advanced laser systems with lower radiation wavelengths, photolithography materials, and mathematical modeling approaches to address the challenges of Cu-interconnect technology.

Technology development needs a market. Since technology development is from supply side, it is always crucial to pay attention to the demand side of technology. Taking this notion as an underlying assumption, this book discusses a technology development case in the realm of microelectronic packaging technology based on a real case study of a three-year consecutive research and development program conducted in Korea with expandable implications for other contexts.

In Advanced ULSI interconnects – fundamentals and applications we bring a comprehensive description of copper-based interconnect technology for ultra-lar- scale integration (ULSI) technology for integrated circuit (IC) application. In- grated circuit technology is the base for all modern electronics systems. You can ?nd electronics systems today everywhere: from toys and home appliances to a- planes and space shuttles. Electronics systems form the hardware that together with software are the bases of the modern information society. The rapid growth and vast exploitation of modern electronics system create a strong demand for new and improved electronic circuits as demonstrated by the amazing progress in the ?eld of ULSI technology. This progress is well described by the famous “Moore’s law” which states, in its most general form, that all the metrics that describe integrated circuit performance (e. g. , speed, number of devices, chip area) improve expon- tially as a function of time. For example, the number of components per chip d- bles every 18 months and the critical dimension on a chip has shrunk by 50% every 2 years on average in the last 30 years. This rapid growth in integrated circuits te- nology results in highly complex integrated circuits with an increasing number of interconnects on chips and between the chip and its package. The complexity of the interconnect network on chips involves an increasing number of metal lines per interconnect level, more interconnect levels, and at the same time a reduction in the interconnect line critical dimensions.