Embedded Multiprocessors

Techniques for Optimizing Multiprocessor Implementations of Signal Processing Applications An indispensable component of the information age, signal processing is embedded in a variety of consumer devices, including cell phones and digital television, as well as in communication infrastructure, such as media servers and cellular base stations. Multiple programmable processors, along with custom hardware running in parallel, are needed to achieve the computation throughput required of such applications. Reviews important research in key areas related to the multiprocessor implementation of multimedia systems Embedded Multiprocessors: Scheduling and Synchronization, Second Edition presents architectures and design methodologies for parallel systems in embedded digital signal processing (DSP) applications. It discusses application modeling techniques for multimedia systems, the incorporation of interprocessor communication costs into multiprocessor scheduling decisions, and a modeling methodology (the synchronization graph) for multiprocessor system performance analysis. The book also applies the synchronization graph model to develop hardware and software optimizations that can significantly reduce the interprocessor communication overhead of a given schedule. Chronicles recent activity dealing with single-chip multiprocessors and dataflow models This edition updates the background material on existing embedded multiprocessors, including single-chip multiprocessors. It also summarizes the new research on dataflow models for signal processing that has been carried out since the publication of the first edition. Harness the power of multiprocessors This book explores the optimization of interprocessor communication and synchronization in embedded multiprocessor systems. It shows you how to design multiprocessor computer systems that are streamlined for multimedia applications.

This book provides a comprehensive overview of the state-of-the-art, data flow-based techniques for the analysis, modeling and mapping technologies of concurrent applications on multi-processors. The authors present a flow for designing embedded hard/firm real-time multiprocessor streaming applications, based on data flow formalisms, with a particular focus on wireless modem applications. Architectures are described for the design tools and run-time scheduling and resource management of such a platform.

High-Performance Embedded Computing, Second Edition, combines leading-edge research with practical guidance in a variety of embedded computing topics, including real-time systems, computer architecture, and low-power design. Author Marilyn Wolf presents a comprehensive survey of the state of the art, and guides you to achieve high levels of performance from the embedded systems that bring these technologies together. The book covers CPU design, operating systems, multiprocessor programs and architectures, and much more. Embedded computing is a key component of cyber-physical systems, which combine physical devices with computational resources for control and communication. This revised edition adds new content and examples of cyber-physical systems throughout the book, including design methodologies, scheduling, and wide-area CPS to illustrate the possibilities of these new systems. Revised and updated with coverage of recently developed consumer electronics architectures and models of computing Includes new VLIW processors such as the TI Da Vinci, and CPU simulation Learn model-based verification and middleware for embedded systems Supplemental material includes lecture slides, labs, and additional resources

Current multimedia and telecom applications require complex, heterogeneous multiprocessor system on chip (MPSoC) architectures with specific communication infrastructure in order to achieve the required performance. Heterogeneous MPSoC includes different types of processing units (DSP, microcontroller, ASIP) and different communication schemes (fast links, non standard memory organization and access). Programming an MPSoC requires the generation of efficient software running on MPSoC from a high level environment, by using the characteristics of the architecture. This task is known to be tedious and error prone, because it requires a combination of high level programming environments with low level software design. This book gives an overview of concepts related to embedded software design for MPSoC. It details a full software design approach, allowing systematic, high-level mapping of software applications on heterogeneous MPSoC. This approach is based on gradual refinement of hardware/software interfaces and simulation models allowing to validate the software at different abstraction levels. This book combines Simulink for high level programming and SystemC for the low level software development. This approach is illustrated with multiple examples of application software and MPSoC architectures that can be used for deep understanding of software design for MPSoC.

Master's Thesis from the year 2007 in the subject Computer Science - Applied, grade: 1.0, Technical University of Munich (Institute for Informatics), 82 entries in the bibliography, language: English, abstract: Multicore systems are dominating the processor market; they enable the increase in computing power of a single chip in proportion to the Moore's law-driven increase in number of transistors. A similar evolution is observed in the system-on-chip (SoC) market through the emergence of multi-processor SoC (MPSoC) designs. Nevertheless, MPSoCs introduce some challenges to the system architects concerning the efficient design of memory hierarchies and system interconnects while maintaining the low power and cost constraints. In this master thesis, I try to address some of these challenges: namely, non-cache coherent DMA transfers in MPSoCs, low instruction cache utilization by OS codes, and factors governing the system throughput in MPSoC designs. These issues are investigated using the empirical and simulation approaches. Empirical studies are conducted on the Danube platform. Danube is a commercial MPSoC platform that is based on two 32-bit MIPS cores and developed by Infineon Technologies AG for deployment in access network processing equipments such as integrated access devices, customer premises equipments, and home gateways. Simulation-based studies are conducted on a system based on the ARM MPCore architecture. Achievements include the successful implementation and testing of novel hardware and software solutions for improving the performance of non-cache coherent DMA transfers in MPSoCs. Several techniques for reducing the instruction cache miss rate are investigated and applied. Finally, a qualitative analysis of the impact of instruction reuse, number of cores, and memory bandwidth on the system throughput in MPSoC systems is presented.

Computers as Components, Second Edition, updates the first book to bring essential knowledge on embedded systems technology and techniques under a single cover. This edition has been updated to the state-of-the-art by reworking and expanding performance analysis with more examples and exercises, and coverage of electronic systems now focuses on the latest applications. It gives a more comprehensive view of multiprocessors including VLIW and superscalar architectures as well as more detail about power consumption. There is also more advanced treatment of all the components of the system as well as in-depth coverage of networks, reconfigurable systems, hardware-software co-design, security, and program analysis. It presents an updated discussion of current industry development software including Linux and Windows CE. The new edition's case studies cover SHARC DSP with the TI C5000 and C6000 series, and real-world applications such as DVD players and cell phones. Researchers, students, and savvy professionals schooled in hardware or software design, will value Wayne Wolf's integrated engineering design approach. * Uses real processors (ARM processor and TI C55x DSP) to demonstrate both technology and techniques...Shows readers how to apply principles to actual design practice. * Covers all necessary topics with emphasis on actual design practice...Realistic introduction to the state-of-the-art for both students and practitioners. * Stresses necessary fundamentals which can be applied to evolving technologies...helps readers gain facility to design large, complex embedded systems that actually work.

Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.

This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors’ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.