Nanoscale Semiconductor Memories

Nanoscale memories are used everywhere. From your iPhone to a supercomputer, every electronic device contains at least one such type. With coverage of current and prototypical technologies, Nanoscale Semiconductor Memories: Technology and Applications presents the latest research in the field of nanoscale memories technology in one place. It also covers a myriad of applications that nanoscale memories technology has enabled. The book begins with coverage of SRAM, addressing the design challenges as the technology scales, then provides design strategies to mitigate radiation induced upsets in SRAM. It discusses the current state-of-the-art DRAM technology and the need to develop high performance sense amplifier circuitry. The text then covers the novel concept of capacitorless 1T DRAM, termed as Advanced-RAM or A-RAM, and presents a discussion on quantum dot (QD) based flash memory. Building on this foundation, the coverage turns to STT-RAM, emphasizing scalable embedded STT-RAM, and the physics and engineering of magnetic domain wall "racetrack" memory. The book also discusses state-of-the-art modeling applied to phase change memory devices and includes an extensive review of RRAM, highlighting the physics of operation and analyzing different materials systems currently under investigation. The hunt is still on for universal memory that fits all the requirements of an "ideal memory" capable of high-density storage, low-power operation, unparalleled speed, high endurance, and low cost. Taking an interdisciplinary approach, this book bridges technological and application issues to provide the groundwork for developing custom designed memory systems.

Knowledge exists: you only have to ?nd it VLSI design has come to an important in?ection point with the appearance of large manufacturing variations as semiconductor technology has moved to 45 nm feature sizes and below. If we ignore the random variations in the manufacturing process, simulation-based design essentially becomes useless, since its predictions will be far from the reality of manufactured ICs. On the other hand, using design margins based on some traditional notion of worst-case scenarios can force us to sacri?ce too much in terms of power consumption or manufacturing cost, to the extent of making the design goals even infeasible. We absolutely need to explicitly account for the statistics of this random variability, to have design margins that are accurate so that we can ?nd the optimum balance between yield loss and design cost. This discontinuity in design processes has led many researchers to develop effective methods of statistical design, where the designer can simulate not just the behavior of the nominal design, but the expected statistics of the behavior in manufactured ICs. Memory circuits tend to be the hardest hit by the problem of these random variations because of their high replication count on any single chip, which demands a very high statistical quality from the product. Requirements of 5–6s (0.

Yield and reliability of memories have degraded with device and voltage scaling in the nano-scale era, due to ever-increasing hard/soft errors and device parameter variations. This book systematically describes these yield and reliability issues in terms of mathematics and engineering, as well as an array of repair techniques, based on the authors’ long careers in developing memories and low-voltage CMOS circuits. Nanoscale Memory Repair gives a detailed explanation of the various yield models and calculations, as well as various, practical logic and circuits that are critical for higher yield and reliability.

Knowledge exists: you only have to ?nd it VLSI design has come to an important in?ection point with the appearance of large manufacturing variations as semiconductor technology has moved to 45 nm feature sizes and below. If we ignore the random variations in the manufacturing process, simulation-based design essentially becomes useless, since its predictions will be far from the reality of manufactured ICs. On the other hand, using design margins based on some traditional notion of worst-case scenarios can force us to sacri?ce too much in terms of power consumption or manufacturing cost, to the extent of making the design goals even infeasible. We absolutely need to explicitly account for the statistics of this random variability, to have design margins that are accurate so that we can ?nd the optimum balance between yield loss and design cost. This discontinuity in design processes has led many researchers to develop effective methods of statistical design, where the designer can simulate not just the behavior of the nominal design, but the expected statistics of the behavior in manufactured ICs. Memory circuits tend to be the hardest hit by the problem of these random variations because of their high replication count on any single chip, which demands a very high statistical quality from the product. Requirements of 5–6s (0.

Today’s semiconductor memory market is divided between two types of memory: DRAM and Flash. Each has its own advantages and disadvantages. While DRAM is fast but volatile, Flash is non-volatile but slow. A memory system based on self-organized quantum dots (QDs) as storage node could combine the advantages of modern DRAM and Flash, thus merging the latter’s non-volatility with very fast write times. This thesis investigates the electronic properties of and carrier dynamics in self-organized quantum dots by means of time-resolved capacitance spectroscopy and time-resolved current measurements. The first aim is to study the localization energy of various QD systems in order to assess the potential of increasing the storage time in QDs to non-volatility. Surprisingly, it is found that the major impact of carrier capture cross-sections of QDs is to influence, and at times counterbalance, carrier storage in addition to the localization energy. The second aim is to study the coupling between a layer of self-organized QDs and a two-dimensional hole gas (2DHG), which is relevant for the read-out process in memory systems. The investigation yields the discovery of the many-particle ground states in the QD ensemble. In addition to its technological relevance, the thesis also offers new insights into the fascinating field of nanostructure physics.

This book summarizes the state-of-the-art, regarding noise in nanometer semiconductor devices. Readers will benefit from this leading-edge research, aimed at increasing reliability based on physical microscopic models. Authors discuss the most recent developments in the understanding of point defects, e.g. via ab initio calculations or intricate measurements, which have paved the way to more physics-based noise models which are applicable to a wider range of materials and features, e.g. III-V materials, 2D materials, and multi-state defects. Describes the state-of-the-art, regarding noise in nanometer semiconductor devices; Enables readers to design more reliable semiconductor devices; Offers the most up-to-date information on point defects, based on physical microscopic models.

This reference text discusses conduction mechanism, structure construction, operation, performance evaluation and applications of nanoscale semiconductor materials and devices in VLSI circuits design. The text explains nano materials, devices, analysis of its design parameters to meet the sub-nano-regime challenges for CMOS devices. It discusses important topics including memory design and testing, fin field-effect transistor (FinFET), tunnel field-effect transistor (TFET) for sensors design, carbon nanotube field-effect transistor (CNTFET) for memory design, nanowire and nanoribbons, nano devices based low-power-circuit design, and microelectromechanical systems (MEMS) design. The book discusses nanoscale semiconductor materials, device models, and circuit design covers nanoscale semiconductor device structures and modeling discusses novel nano-semiconductor devices such as FinFET, CNTFET, and Nanowire covers power dissipation and reduction techniques Discussing innovative nanoscale semiconductor device structures and modeling, this text will be useful for graduate students, and academic researchers in diverse areas such as electrical engineering, electronics and communication engineering, nanoscience, and nanotechnology. It covers nano devices based low-power-circuit design, nanoscale devices based digital VLSI circuits, and novel devices based analog VLSI circuits design.

Semiconductor Memories provides in-depth coverage in the areas of design for testing, fault tolerance, failure modes and mechanisms, and screening and qualification methods including. * Memory cell structures and fabrication technologies. * Application-specific memories and architectures. * Memory design, fault modeling and test algorithms, limitations, and trade-offs. * Space environment, radiation hardening process and design techniques, and radiation testing. * Memory stacks and multichip modules for gigabyte storage.